MSE PRO Customized Silicon-on-Insulator (SOI) Wafer (4"-8")
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Silicon-on-Insulator (SOI) wafer is a structure including the device layer (top), buried oxide layer (middle), and handle wafer (bottom). This technology allows for the continuous miniaturization of microelectronic devices. It has several advantages over a traditional silicon wafer, like low leakage currents and low parasitic capacitance. It is used in various applications, including MEMS, sensors, telecommunications, and power devices. For example, the researchers at Toyota Central R&D Labs proposed simple T-shaped support as a solution to the tilt deformation caused by the residual stress. This solution could potentially allow for the development of high-precision sensors and actuators.
Types of SOI Wafers:
SIMOX: Device Layer Thickness < 250nm
BESOI: Device Layer Thickness between 1 μm ~ 300μm
SIMBOND: Device Layer Thickness < 200nm
Smart-Cut: Device Layer Thickness < 1.5μm
Capability:
| Parameter | Specification Range |
| Diameter | 100 ~ 200mm |
| Device Layer | |
| Thickness | 0.1 ~ 300μm |
| Type |
P or N (please specify if you need certain dopant) |
| Orientation | (100) or (111) or (110) |
| Box Layer | |
| Thickness | up to 3.5μm |
| Uniformity | ± 2.5% |
| Handle Wafer | |
| Type |
P or N (please specify if you need certain dopant) |
| Resistivity | Customized |
*The figure is for reference only. The actual product may look different due to configuration difference.
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