MSE PRO 4 inch p-type Silicon-on-Insulator (SOI) Wafer <100> (Device: 5μm; Box: 1μm)

MSE PRO 4 inch p-type Silicon-on-Insulator (SOI) Wafer <100> (Device: 5μm; Box: 1μm)

Limited quantities in stock. Please contact us for the current inventory. 

Introduction 

Silicon on Insulator (SOI) represents a breakthrough in semiconductor wafer technology, outperforming traditional bulk silicon methods. By introducing a thin insulating layer (box layer), typically silicon oxide, between a layer of silicon (top, device layer) and the silicon (bottom, handle layer) substrate, SOI significantly reduces junction capacitance. This results in dynamic devices that are up to 15 percent faster and consume 20 percent less power compared to conventional bulk complementary metal-oxide semiconductor (CMOS)-based chips.

The impact of SOI extends across diverse industries due to its ability to enhance electronic device efficiency. It finds applications in high-performance computing, telecommunications, automotive, and the Internet of Things (IoT). SOI wafers are integral to advancing cutting-edge technologies, providing remarkable speed and power-saving capabilities.

Specifications

*The figure is for reference only. The actual product may look different due to configuration difference.
Please  contact us if you need to place bulk orders or need customization.

References:

1. The Genesis Process/sup TM: a new SOI wafer fabrication method. In 1998 IEEE International SOI Conference Proceedings (Cat No. 98CH36199), pp. 163-164. IEEE, 1998.

2. Layout controlled one-step dry etch and release of MEMS using deep RIE on SOI wafer. Journal of microelectromechanical systems 15, no. 3 (2006): 541-547

3. Improved anchor design for flat MEMS structure by suppressing deformation due to buried-oxide stress on silicon-on-insulator wafer. Journal of Micromechanics and Microengineering 31, no. 4 (2021): 045001.