Silicon on Sapphire (SOS) wafers usually comprised of R-Plane (1102) sapphire wafers with a deposited layer of silicon on their polished surface. The sapphire wafer at the bottom of the structure has high permittivity, which can reduce the leakage current, parasitic components, and power consumption. Combining the advantage of silicon and sapphire, SOS wafer provides outstanding isolation and reduces the parasitic capacitance at the bottom of the PN junction. SOS wafers outperforms Silicon-on-Insulator (SOI) wafer when used in mobile devices and other electronics, where low power consumption and resistance to radiation is required. It is often used in various integrated circuits, including large scale integrated circuits and radio frequency integrated circuits (RFIC).

Specification:

Substrate:

Material	Single Crystal Al₂O₃ (Sapphire)
Orientation	customized
Diameter	customized
Thickness	customized
Surface	SSP/DSP

Epitaxial Layer:

Composition	Silicon
Thickness	customized
Silicon Orientation	(100)
Type/Dopant	Intrinsic/Undoped
Particles	(for particles > 2um): < 2 per cm²

References:

1. Silicon-on-sapphire integrated waveguides for the mid-infrared. Optics express 18, no. 12 (2010): 12127-12135.

2. The state-of-the-art of silicon-on-sapphire CMOS RF switches. In IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC'05., pp. 4-pp. IEEE, 2005.